Binary data transfer apparatus



April 23, 1963 R. D. BUCK BINARY DATA TRANSFER APPARATUS 2 Sheets-Sheet2 Filed March 16, 1960 assists Patented Apr. 23, 1963 3,687,142 BKNARYDATA TRANSFER AIWARATEJS Robert D. lliucir, Saugerties, N.Y., assignorto international Business Machines Corporation, New York, N.Y., acorporation of New York Filed Mar. 16, 196i), Ser. No. 15,237 '7 Claims.(Ci. 3443-1147) This invention relates generally to electronic computingmachines, and in particular it is concerned with the sampling ofnumerous sources of data which is to be assimilated by such machines.

Data may be supplied to computing machines from multiple sources whichrequire reading periods to sense the data that are much longer than thetime needed by the computer to assimilate the sensed data in serialform. Consequently, if the computer must wait for successive sensing ofsuch sources for its data supply, its operation may be slowed and itseificiency undesirably reduced.

The primary object of the present invention is to provide a system forsampling data from multiple sources of this type and to supply thesampled data as input data to an electronic computer in a time intervalmuch shorter than the aggregate of the sensing periods for each source.Other objects are to provide a high speed sampling system for such datawhich is highly reliable yet economical in the use of equipment toimplement it.

In brief, the system of the present invention makes use of a number ofcommutator type selector switches which are driven in synchronism. Eachof the switches ser es to select successive ones of a correspondinggroup of data signal sources for connection to a threshold comparatorunit. The output of each comparator in turn is applied to a gate whichis conditioned to pass a signal from the com-4 parator to a computeronly for a very brief interval repre senting but a fraction of the timeduring which the comparator is connected to a signal source. In this wayeach of the comparators is adapted to be momentarily coupled to thecomputer once during each step of the commutator switches.

The novel features of the invention together with further objects andadvantages thereof will become apparent from the following detaileddescription and the drawing to which it refers.

In the drawing:

FIG. 1 is a block diagram illustrating the switching logic of the systemaccording to the present invention, and

FIG. 2 is a block diagram illustrating the timing logic of the system.

With reference first to FIG. 1 it will be observed that the illustratedembodiment of the invention contemplates the transfer of data from 1024separate signal sources represented by terminals 1-16 and 1817-1624 inthe drawing. Not shown are terminals 17-1916 in order to simplify thedrawing and make it easier to understand the underlying principles ofthe invention. Connected to each of the terminals is a correspondingswitch contact of like number with a prime added. These contacts, whichare accordingly numbered l'-16 and H917- ltiZd, together with movablearms 21-23, comprise a group of eight commutator type selector switchesdriven from a commutator shaft indicated diagramatically atSpecifically, a first of these selector switches includes contacts i,9', 1.117 and arm 21; a second of these switches includes contacts 2,16, 1 518 and arm 22, and so forth. The eifective arcuate dimensions ofthe arms are seen to be slightly less than the spacing between adiacentcontacts on the switches. The significance of this fact and the factthat the respective arms exhibit a progressive shift in angular positionwill be explained in detail hereinafter.

Connected to the respective movable arms of the switches are thresholdcomparator units 31-38 and connected to the output sides of thecomparator units are pulse gates 41-48. The comparator units 31-38 serveto re-transmit data signals if the magnitudes of the signals exceed apredetermined amount. Units of this kind are well known and areavailable commercially. They may comprise conventional trigger circuits,for example. The pulse gates serve to pass the re-transmitted signalsone after another to an OR circuit St in response to sequential pulsesignals on lines 51-58. The nature of these pulse signals and the mannerin which they are produced will be described in detail in connectionwith FIG. 2.

With reference now to FIG. 2 it will be observed that in addition to theselector switches shown in FIG. 1, the commutator shaft 3i? drives asynchronized switch arm 6%. Switch arm 6t? cooperates with stationarycontacts Er k-123A to produce synchronizing pulses of current from abattery 61, it being understood that the battery is merely illustrativeof an energy source. The synchronizing pulses, in turn, are applied to adelay unit 64 by way of a pulse shaping circuit 62 and a logical ORcircuit 63. The output side of delay unit 54 is connected to a similardelay unit 65 which has its output side coupled to both theaforementioned OR circuit 63, through a gate as, and to a scale of eightcounting circuit.

The counting circuit is seen to comprise a pair of gates 7e, 77 andflipflops 71-73 having complementing inputs and ONE and ZERO outputs.Incoming pulses from delay unit 65 are applied to the complementinginput of flip-flop 71 and to the gate 76. Gate 76 is conditioned by theone side of Hip-Hop 71 to pass on the pulse to the complementing inputof flip-flop '72 and to the input of gate 77. Gate 77, in turn, passesthe pulse to flip-flop 73 whenever the gate is conditioned by the oneside of flipflop '72.

The count carried by the flip-flops is used to condition sequentially agroup of eight gates 81-83. To this end, a group of eight logical ANDcircuits 91-?3 is provided, each of which has three inputs served by aunique combination of outputs from the flip-flops. For

sample AND circuit 91 has its inputs connected to the ZERO sides of theflip-flops; AND circuit $2 has its inputs connected to the ONE side ofthe flip-flop 7i and to the ZERO sides of flip-flops 72 and 73, and soforth. The outputs of the respective AND circuits serve to condition thegates 31-88 which, as shown, are sensed by pulses from delay unit 64.Completing the timing arrangement of FIG. 2 is a logical OR circuit h?which is served with conditioning levels for the gate 66 by the ZEROsides of flips-flops 71-73.

In operation the amount of delay introduced by elements 64 and 65 isapproximately equivalent to oneeighth of the period between pulses fromthe synchronizer switch. Consequently, each switch pulse is fed back byway of gate circuit 66 and caused to reappear at the output of element65 seven times before the occurrence of the next switch pulse. Upon theoccurrence of an original switch pulse and seven such following pulses,all of the flip-flops are placed in a ONE state representing a fullcount. In consequence, gate 66 becomes deconditioned so that the nextgroup of eight such pulses will be initiated by the action of thesynchronizer switch alone.

As should by now be apparent, the object of this arrangement is theprovision of synchronized timing pulses which have a repetition rateeight times as fast as that of the switch pulses. These timing pulsessense gates 31-88 which, as aforementioned, are sequentially conditionedby the AND circuits 91-9 8 according to the count in the flip-flops.Gates 81-88 are thus adapted to serve as separate sources of timingpulses, each gate providing one pulse in every group of eight thatoccurs.

With reference now once again to FIG. 1, it will be observed that therespective switch arms 21-28 are in registry with contacts 1-8 to whichterminals 1-8 are connected. However, it will also be observed thatswitch arm 21 is about to break with con-tact 1, whereas switch arm 28has just begun to make with contact 8', the other switch arms 22-28assuming graduated angular positions in between. Thus, if it be assumedthat a signal has been caused to appear at each of the first eightterminals, all of the threshold comparator units will have signalsapplied to them during successive inrtervals that overlap one another.The signals from the threshold comparators, however, are gated outduring successive intervals that are distinct. In particular, with thecontact arms in the positions shown, gate 41 is the first gate to besensed because arm 21 is just completing its period of contact duringwhich corresponding comparator unit 31 is receiving the incoming signal.When arm 22 arrives at a position corresponding to that shown for arm21, gate 42 is the next to be sensed and so forth. It follows thatbefore each of the gates is opened to pass a signal from a thresholdcomparator unit, the latter will have been connected to one of thesource terminals for the full period of contact of the selector switcharms. Since it is contemplated that the system of the invention will beused with data signals of varying amplitude characteristics and thatonly those signals whose amplitudes exceed a predetermined level will bepassed by the comparator units, this period of contact is extremelysignificant =for without it the comparator units could not properlyreact to the data signals. There is no such restriction on the outputsignals from the comparator units themselves, however, because these areall of uniform amplitude sufiicient to be readily recognizable by acomputer or other utilization device. According to the invention,therefore, data signals can be made available to a cumputer successivelyat a much faster rate than the aggregate time provided for deriving thesignals from the terminals of the individual sources, using butrelatively little data transfer equip ment. If instead, commutator typeswitching were employed throughout, the rate of data transfer would haveto be much lower.

While a single preferred embodiment of the invention has been shown anddescribed herein, various modifications thereof will be obvious to thoseskilled in the art and it will be understood that the invention is notintended to be limited thereto or to details thereof and departures maybe made therefrom within the spirit and scope of the invention asdefined in the claims.

What is claimed is:

1. A high speed sampling system for sampling parallel input data signalsapplied on a multiplicity of input lines and translating those appliedinput data signals which meet a pro-established criterion in sequenceinto an output circuit, comprising a predetemined number ofelectromechanical selector switches, said predetermined number beingsmaller than the number of input lines, each said selector switch havinga corresponding plurality of first contacts and a second contact movablerelative to said first contacts to make and break circuit with saidfirst contacts in sequence, a sampling signal generator including aswitch component having a plurality of contact members corresponding in.number to the number of said first contacts on each of said selectorswitches and correspondingly positioned on said switch component, and acooperating contact member movable relative to said contact members tosequentially make and break circuit with said contact members to producesampling signals, said switch component and said selector switches beingganged so that said cooperating contact member and all of said secondcontacts are moved relative to their associated contact members andfirst contacts at the same time and at the same rate, each of said inputlines being connected to a difierent one of said first contacts, asignal discriminator circuit connected toeach said second con tact andadapted to produce an output signal whenever the signal applied to saiddiscriminator circuit from the connected second contact meets saidpre-est-ablished criterion, a gate connected to each said discriminatorcircuit for controlling the transmission of output signals from saiddiscriminator circuit to said output circuit, means to apply gatesampling signals from said sampling signal generator to said gates insequence, and a driver for moving said second contacts and saidcooperating contact member relative to said first contacts and saidcontact members in unison.

2. A sampling system as claimed in claim 1 wherein said selectorswitches :are continuously driven and said first contacts are stationarycontacts and said second contacts are movable contacts which dwell onsaid stationary contacts during overlapping intervals of time to applysaid input data signals to the associated discriminator circuit duringsaid overlapping intervals of time.

3. A sampling system as claimed in claim 2 wherein said sampling pulsegenerator further includes an oscillatory device to produce timingpulses, means responsive to said sampling signals to synchronize theoperation of said device with the speed of operation of said switches,and means to count timing pulses produced by said device, and whereinsaid means to apply gate sampling signals is operative in accordancewith the count held by said counting means.

4. A sampling system for parallel data signals comprising a group ofcontinuously operable selector switches, each of said switches having aplurality of angularly spaced stationary contacts and at least onerelatively movable contact which dwells on successive ones of saidstationary contacts for equal time intervals, said switches having theirmovable contacts disposed in relatively different angular positions,said positions differing uniformly fromswitch to switch by an amountcorresponding to equal fractions of an interval, a corresponding groupof threshold comparator units to produce output signals when theamplitudes of the applied data signals exceed a predetermined amplitude,said data signals being successively applied to said comparator units bymeans of said switches, a corresponding group of gate circuitsselectively to pass the output signals produced by said comparisondevices, switch means mechanically coupled to said switches to generatea train of synchronizing pulses, oscillatory apparatus to generate atrain of timing pulses, the repetition rate of said timing pulses beingsynchronized with the speed of said switches by means of saidsynchronizing pulses, and means individually to apply the timing pulsesto said gate circuits in a predetermined sequence.

5. A high speed sampling system for sampling parallel input data signalsapplied on a multiplicity of input lines and translating those appliedinput data signals which meet a pre-established criterion in sequenceinto an output circuit, comprising a predetermined number ofelectromechanical selector switches, said predetermined number beingsmaller than the number of input lines, each said selector switch havinga corresponding plurality of angu larly spaced stationary first contactsand a continuously movable second contact which makes and breaks circuitwith said stationary contacts in sequence, and dwells on successive onesof said stationary contacts for equal time intervals, a sampling signalgenerator including a switch component having a plurality of stationarycontact members corresponding in number to the number of said firstcontacts on each of said selector switches and correspondingly angularlypositioned on said switch component, and a continuously movablecooperating contact member which sequentially makes and breaks circuitwith said contact members to produce sampling signals, said switchcomponent and said selector switches being ganged so that saidcooperating contact member and all of said second contacts are movedrelative to their associated contact members and first contacts at thesame time and at the same rate, each of said input lines being connectedto a different one of said first contacts, a signal discriminatorcircuit connected to each said second contact and adapted to produce anoutput signal whenever the signal applied to said discriminator circuitfrom the connected second contact meets said pre-established criterion,a gate connected to each said discriminator circuit for controlling thetransmission of output signals from said discriminator circuit to saidoutput circuit, means to apply gate sampling sigmails from said samplingsignal generator to said gates in sequence, and a driver forcontinuously moving said movable contacts and said cooperating contactmember relative to said stationary contacts and said stationary contactmembers in unison.

6'. A high speed data signal input system for translating parallel inputdata signals applied on a multiplicity of input lines into an outputcircuit, comprising a predetermined number of electromechanical selectorswitches, said predetermined number being smaller than the number ofinput lines, each said selector switch having a corresponding pluralityof first contacts and a second contact movable relative to said firstcontacts to make and break circuit with said first contacts in sequence,a sampling signal generator including a switch component hav. ing aplurality of contact members corresponding in number to the number ofsaid first contacts on each of said selector switches andcorrespondingly positioned on said switch component, and a cooperatingcontact member movable relative to said contact members to sequentiallymake and break circuit with said contact members to produce samplingsignals, said switch component and said selector switches being gangedso that said cooperating contact member and all of said second contactsare moved relative to their associated contact members and firstcontacts at the same time and at the same rate, each of said input linesbeing connected to a different one of said first contacts, a gateassociated with each said second contact and responsive to input signalson the associated second contact for controlling the transmission ofsignals from said associated second contact to said output circuit,means to apply gate sampling signals from said sampling signal generatorto said gates in sequence, and a driver for moving said second contactsand said cooperating contact member relative to said first contacts andsaid contact members in unison.

7. The system as claimed in claim 6 wherein said sampling signalgenerator further includes oscillatory apparatus to generate a train ofpulses in response to each sampling signal from said cooperating contactmember, the number of pulses in each said train being equal to saidpredetermined number, and counter means operative to distribute thepulses in each train for application to said gates in sequence.

References Cited in the file of this patent UNITED STATES PATENTS2,899,567 Romano Aug. 11, 1959

4. A SAMPLING SYSTEM FOR PARALLEL DATA SIGNALS COMPRISING A GROUP OFCONTINUOUSLY OPERABLE SELECTOR SWITCHES, EACH OF SAID SWITCHES HAVING APLURALITY OF ANGULARLY SPACED STATIONARY CONTACTS AND AT LEAST ONERELATIVELY MOVABLE CONTACT WHICH DWELLS ON SUCCESSIVE ONES OF SAIDSTATIONARY CONTACTS FOR EQUAL TIME INTERVALS, SAID SWITCHES HAVING THEIRMOVABLE CONTACTS DISPOSED IN RELATIVELY DIFFERENT ANGULAR POSITIONS,SAID POSITIONS DIFFERING UNIFORMLY FROM SWITCH TO SWITCH BY AN AMOUNTCORRESPONDING TO EQUAL FRACTIONS OF AN INTERVAL, A CORRESPONDING GROUPOF THRESHOLD COMPARATOR UNITS TO PRODUCE OUTPUT SIGNALS WHEN THEAMPLITUDES OF THE APPLIED DATA SIGNALS EXCEED A PREDETERMINED AMPLITUDE,SAID DATA SIGNALS BEING SUCCESSIVELY APPLIED TO SAID COMPARATOR UNITS BYMEANS OF SAID SWITCHES, A CORRESPONDING GROUP OF GATE CIRCUITSSELECTIVELY TO PASS THE OUTPUT SIGNALS PRODUCED BY SAID COMPARISONDEVICES, SWITCH MEANS MECHANICALLY COUPLED TO SAID SWITCHES TO GENERATEA TRAIN OF SYNCHRONIZING PULSES, OSCILLATORY APPARATUS TO GENERATE ATRAIN OF TIMING PULSES, THE REPETITION RATE OF SAID TIMING PULSES BEINGSYNCHRONIZED WITH THE SPEED OF SAID SWITCHES BY MEANS OF SAIDSYNCHRONIZING PULSES, AND MEANS INDIVIDUALLY TO APPLY THE TIMING PULSESTO SAID GATE CIRCUITS IN A PREDETERMINED SEQUENCE.